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3.3 ghz ultralow distortion rf/if differential amplifier adl5562 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2010 analog devices, inc. all rights reserved. features ?3 db bandwidth of 3.3 ghz (a v = 6 db) pin-strappable gain adjust: 6 db, 12 db, 15.5 db differential or single-ended input to differential output low noise input stage: 2.1 nv/hz rti @ a v = 12 db low broadband distortion (av = 6 db) 10 mhz: ?91 dbc hd2, ?98 dbc hd3 70 mhz: ?102 dbc hd2, ?90 dbc hd3 140 mhz: ?104 dbc hd2, ?87 dbc hd3 250 mhz: ?80 dbc hd2, ?94 dbc hd3 imd3s of ?94 dbc at 250 mhz center slew rate: 9.8 v/ns fast settling of 2 ns and overdrive recovery of 3 ns single-supply operation: 3 v to 3.6 v power-down control fabricated using the high speed xfcb3 sige process applications differential adc drivers single-ended to differential conversion rf/if gain blocks saw filter interfacing functional block diagram vip2 enbl r f r f vcom vop vip1 v in1 v in2 adl5562 08003-001 gnd v cc von r g2 r g1 r g1 r g2 figure 1. general description the adl5562 is a high performance differential amplifier optimized for rf and if applications. the amplifier offers low noise of 2.1 nv/hz and excellent distortion performance over a wide frequency range, making it an ideal driver for high speed 8-bit to 16-bit adcs. the adl5562 provides three gain levels of 6 db, 12 db, and 15.5 db through a pin-strappable configuration. for the single- ended input configuration, the gains are reduced to 5.6 db, 11.1 db, and 14.1 db. using an external series input resistor expands the amplifier gain flexibility and allows for any gain selection from 0 db to 15.5 db. the quiescent current of the adl5562 is typically 80 ma and, when disabled, consumes less than 3 ma, offering excellent input-to-output isolation. the device is optimized for wideband, low distortion performance. these attributes, together with its adjustable gain capability, make this device the amplifier of choice for general-purpose if and broadband applications where low distortion, noise, and power are critical. this device is optimized for the best combination of slew speed, bandwidth, and broadband distortion. these attributes allow it to drive a wide variety of adcs and make it ideally suited for driving mixers, pin diode attenuators, saw filters, and multi- element discrete devices. fabricated on an analog devices, inc., high speed sige process, the adl5562 is supplied in a compact 3 mm 3 mm, 16-lead lfcsp package and operates over the temperature range of ?40c to + 85c.
adl5562 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 circuit description ......................................................................... 13 basic structure ............................................................................ 13 applications information .............................................................. 14 basic connections ...................................................................... 14 input and output interfacing ................................................... 15 gain adjustment and interfacing ............................................ 16 adc interfacing ......................................................................... 16 layout considerations ............................................................... 18 soldering information ............................................................... 19 evaluation board ........................................................................ 19 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 3/10rev. a to rev. b changes to figure 43 ...................................................................... 19 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 9/09rev. 0 to rev. a changes to features section............................................................ 1 changes to table 1 ............................................................................ 3 changes to figure 5 .......................................................................... 8 changes to figure 9 and figure 10 ................................................. 9 changes to figure 32, equation 1, and figure 34....................... 15 changes to equation 2 ................................................................... 16 changes to figure 38, figure 39, figure 40, and table 9 ........... 17 changes to figure 43 ...................................................................... 19 moved table 14 to .......................................................................... 19 5/09revision 0: initial version
adl5562 rev. b | page 3 of 24 specifications vcc = 3.3 v, vcom = 1.65 v, r l = 200 differential, a v = 6 db, c l = 1 pf differential, f = 140 mhz, t a = 25c. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth a v = 6 db, v out 1.0 v p-p 3300 mhz a v = 12 db, v out 1.0 v p-p 3900 mhz a v = 15.5 db, v out 1.0 v p-p 1900 mhz bandwidth for 0.1 db flatness a v = 6 db, v out 1.0 v p-p 220 mhz a v = 12 db, v out 1.0 v p-p 270 mhz a v = 15.5 db, v out 1.0 v p-p 270 mhz gain accuracy a v = 6 db, r l = open 0.17 db a v = 12 db, r l = open 0.05 db a v = 15.5 db, r l = open 0.06 db gain supply sensitivity vcc 5% ?0.005 db/v gain temperature sensitivity ?40c to +85c, a v = 15.5 db 0.32 mdb/c slew rate rise, a v = 15.5 db, r l = 200 , v out = 2 v step 9.8 v/ns fall, a v = 15.5 db, r l = 200 , v out = 2 v step 10.1 v/ns settling time 2 v step to 1% 2 ns overdrive recovery time v in = 4 v to 0 v step, v out 10 mv 3 ns reverse isolation (s12) 60 db input/output characteristics output common mode vcc/2 v voltage adjustment range 1.4 to 1.8 v maximum output voltage swing 1 db compressed 4.9 v p-p output common-mode offset referenced to vcc/2 60 mv output common-mode drift ?40c to +85c 285 v/c output differential offset voltage 1 mv cmrr 65 db output differential offset drift ?40c to +85c 15 v/c input bias current 3 a input resistance (differential) a v = 6 db 400 a v = 12 db 200 a v = 15.5 db 133 input resistance (single-ended) 1 a v = 5.6 db, r s = 50 307 a v = 11.1 db, r s = 50 179 a v = 14.1 db, r s = 50 132 input capacitance (single-ended) 0.3 pf output resistance (differential) 12 power interface supply voltage 3 3.3 3.6 v enbl threshold device disabled, enbl low 0.6 v device enabled, enbl high 1.3 v enbl input bias current enbl high ?27 a enbl low ?300 a quiescent current enbl high 75.5 80 84.5 ma enbl low 3.5 ma
adl5562 rev. b | page 4 of 24 parameter conditions min typ max unit 10 mhz noise/harmonic performance second/third harmonic distortion a v = 6 db, r l = 200 , v out = 2 v p-p ?91/?98 dbc a v = 12 db, r l = 200 , v out = 2 v p-p ?95/?98 dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p ?96/?92 dbc output third-order intercept/third-order intermodulation distortion a v = 6 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +42/?97 dbm/dbc a v = 12 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +43/?93 dbm/dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +43/?91 dbm/dbc noise spectral density (rti) a v = 6 db 3 nv/hz a v = 12 db 2.1 nv/hz a v = 15.5 db 1.6 nv/hz 1 db compression point (rto) a v = 6 db 19.7 dbm a v = 12 db 19.6 dbm a v = 15.5 db 18.2 dbm 70 mhz noise/harmonic performance second/third harmonic distortion a v = 6 db, r l = 200 , v out = 2 v p-p ?102/?90 dbc a v = 12 db, r l = 200 , v out = 2 v p-p ?97/?85 dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p ?93/?83 dbc output third-order intercept/third-order intermodulation distortion a v = 6 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +46/?96 dbm/dbc a v = 12 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +44/?93 dbm/dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +43/?91 dbm/dbc noise spectral density (rti) a v = 6 db 3 nv/hz a v = 12 db 2.1 nv/hz a v = 15.5 db 1.6 nv/hz 1 db compression point (rto) a v = 6 db 19.6 dbm a v = 12 db 19.6 dbm a v = 15.5 db 18.2 dbm 140 mhz noise/harmonic performance second/third harmonic distortion a v = 6 db, r l = 200 , v out = 2 v p-p ?104/?87 dbc a v = 12 db, r l = 200 , v out = 2 v p-p ?82/?81 dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p ?80/?80 dbc output third-order intercept/third-order intermodulation distortion a v = 6 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +47/?100 dbm/dbc a v = 12 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +45/?95 dbm/dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +43/?92 dbm/dbc noise spectral density (rti) a v = 6 db 3 nv/hz a v = 12 db 2.1 nv/hz a v = 15.5 db 1.6 nv/hz 1 db compression point (rto) a v = 6 db 19.6 dbm a v = 12 db 19.4 dbm a v = 15.5 db 18.1 dbm
adl5562 rev. b | page 5 of 24 parameter conditions min typ max unit 250 mhz noise/harmonic performance second/third harmonic distortion a v = 6 db, r l = 200 , v out = 2 v p-p ?80/?94 dbc a v = 12 db, r l = 200 , v out = 2 v p-p ?74/?86 dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p ?74/?84 dbc output third-order intercept/third-order intermodulation distortion a v = 6 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +43/?94 dbm/dbc a v = 12 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +41/?87 dbm/dbc a v = 15.5 db, r l = 200 , v out = 2 v p-p composite (2 mhz spacing) +40/?86 dbm/dbc noise spectral density (rti) a v = 6 db 3.2 nv/hz a v = 12 db 2.2 nv/hz a v = 15.5 db 1.6 nv/hz 1 db compression point (rto) a v = 6 db 19.8 dbm a v = 12 db 19.3 dbm a v = 15.5 db 19.1 dbm 500 mhz noise/harmonic performance second/third harmonic distortion a v = 6 db, r l = 200 , v out = 1 v p-p ?75/?69 dbc a v = 12 db, r l = 200 , v out = 1 v p-p ?69/?73 dbc a v = 15.5 db, r l = 200 , v out = 1 v p-p ?72/?75 dbc output third-order intercept/third-order intermodulation distortion a v = 6 db, r l = 200 , v out = 1 v p-p composite (2 mhz spacing) +40/?98 dbm/dbc a v = 12 db, r l = 200 , v out = 1 v p-p composite (2 mhz spacing) +39/?97 dbm/dbc a v = 15.5 db, r l = 200 , v out = 1 v p-p composite (2 mhz spacing) +38/?93 dbm/dbc noise spectral density (rti) a v = 6 db 3.7 nv/hz a v = 12 db 2.2 nv/hz a v = 15.5 db 1.6 nv/hz 1 db compression point (rto) a v = 6 db 18.1 dbm a v = 12 db 18.1 dbm a v = 15.5 db 18.1 dbm 1000 mhz noise/harmonic performance second/third harmonic distortion a v = 6 db, r l = 200 , v out = 1 v p-p ?70/?60 dbc a v = 12 db, r l = 200 , v out = 1 v p-p ?69/?61 dbc a v = 15.5 db, r l = 200 , v out = 1 v p-p ?66/?59 dbc output third-order intercept/third-order intermodulation distortion a v = 6 db, r l = 200 , v out = 1 v p-p composite (2 mhz spacing) +24/?65 dbm/dbc a v = 12 db, r l = 200 , v out = 1 v p-p composite (2 mhz spacing) +24/?66 dbm/dbc a v = 15.5 db, r l = 200 , v out = 1 v p-p composite (2 mhz spacing) +25/?66 dbm/dbc noise spectral density (rti) a v = 6 db 4.7 nv/hz a v = 12 db 2.2 nv/hz a v = 15.5 db 1.6 nv/hz 1 db compression point (rto) a v = 6 db 15 dbm a v = 12 db 15.1 dbm a v = 15.5 db 15.1 dbm 1 see the section for a discussion of single-ended input, dc-coupled operation. applications information
adl5562 rev. b | page 6 of 24 absolute maximum ratings table 2. parameter rating supply voltage (vcc) 3.6 v vip1, vip2, vin1, vin2 vcc + 0.5 v internal power dissipation 310 mw ja 98.3c/w maximum junction temperature 125c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adl5562 rev. b | page 7 of 24 pin configuration and fu nction descriptions pin 1 indicator 1 vip2 2 vip1 3 vin1 4 vin2 11 vop 12 enbl 10 von 9vcom 5 v c c 6 v c c 7 v c c 8 v c c 1 5 g n d 1 6 g n d 1 4 g n d 1 3 g n d top view (not to scale) adl5562 08003-031 notes 1. exposed paddle. connect to a low impedance thermal and electrica l ground plane. figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 vip2 balanced differential input. biased to vcom, typically ac-coupled. input for a v = 12 db gain, strapped to vip1 for a v = 15.5 db. 2 vip1 balanced differential input. biased to vcom, typically ac-coupled. input for a v = 6 db gain, strapped to vip2 for a v = 15.5 db. 3 vin1 balanced differential input. biased to vcom, typically ac-coupled. input for a v = 6 db gain, strapped to vin2 for a v = 15.5 db. 4 vin2 balanced differential input. biased to vcom, typically ac-coupled. input for a v = 12 db gain, strapped to vin1 for a v = 15.5 db. 5, 6, 7, 8 vcc positive supply. 9 vcom common-mode voltage. a voltage applied to this pi n sets the common-mode voltage of the input and output. typically decoupled to ground with a 0.1 f capacitor. with no reference applied, input and output common mode floats to midsupply (vcc/2). 10 von balanced differential output. bi ased to vcom, typically ac-coupled. 11 vop balanced differential output. bi ased to vcom, typically ac-coupled. 12 enbl enable. apply positive voltage (1.0 v < enbl < vcc) to activate device. 13, 14, 15, 16 gnd ground. connect to low impedance ground. ep exposed pad. connect to a low impedance thermal and electrical ground plane.
adl5562 rev. b | page 8 of 24 typical performance characteristics vcc = 3.3 v, vcom = 1.65 v, r l = 200 differential, a v = 6 db, c l = 1 pf differential, f = 140 mhz, t = 25c. 4 6 8 10 12 14 16 10m 100m 1g 10g gain (db) maximum gain mid gain minimum gain frequency (hz) 08003-002 ?40c +25c +85c figure 3. gain vs. frequency response for 200 differential load, a v = 6 db, a v = 12 db, and a v = 15.5 db over temperature 10m 100m 1g 10g frequency (hz) 08003-003 4 6 8 10 12 14 16 18 20 gain (db) maximum gain mid gain minimum gain ?40c +25c +85c figure 4. gain vs. frequency response for 1 k differential load, a v = 6 db, a v = 12 db, and a v = 15.5 db over temperature 0 2 4 6 8 10 12 14 16 10 100 1000 noise figure (db) frequency (mhz) a v maximum a v mid a v minimum 08003-004 figure 5. noise figure vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db 5 10 15 20 25 0 100 200 300 400 500 600 700 800 900 1000 op1db (dbm) freqeuncy (mhz) min gain +85c min gain +25c min gain ?40c mid gain +85c mid gain +25c mid gain ?40c max gain +85c max gain +25c max gain ?40c r l = 200 ? 0 8003-016 figure 6. output p1db (op1db) vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db over temperature, 200 differential load 5 10 15 20 25 0 100 200 300 400 500 600 700 800 900 1000 op1db (dbm) frequency (mhz) min gain +85c min gain +25c min gain ?40c mid gain +85c mid gain +25c mid gain ?40c max gain +85c max gain +25c max gain ?40c 08003-017 r l = 1k ? figure 7. output p1db (op1db) vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db over temperature, 1 k differential load 0 1 2 3 4 5 6 7 8 10m 100m 1g noise spectr a l density (nv/ hz) frequency (hz) a v maximum a v mid a v minimum 08003-005 figure 8. noise spectral density vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db
adl5562 rev. b | page 9 of 24 10 15 20 25 30 35 40 45 50 55 60 0 50 100 150 200 250 oip3 (dbm) frequency (mhz) a v maximum a v mid a v minimum 08003-018 figure 9. output third-order intercept at three gains, output level at 2 v p-p composite, r l = 200 0 10 20 30 40 50 60 0 50 100 150 200 250 oip3 (dbm) frequency (mhz) +85c +25c ?40c 08003-019 figure 10. output third-order intercept vs. frequency, over temperature, output level at 2 v p-p composite, r l = 200 30 35 40 45 50 55 60 0 50 100 150 200 250 oip3 (dbm) frequency (mhz) a v maximum a v mid a v minimum 08003-006 figure 11. oip3 vs. freque ncy (single-ended input) ?120 ?100 ?80 ?60 ?40 ?20 0 ?160 ?140 ?120 ?100 ?80 ?60 ? 40 0 50 100 150 200 250 imd3, r l = 1k ? (dbc) imd3, r l = 200 ? (dbc) frequency (mhz) a v maximum a v mid a v minimum 08003-020 figure 12. two-tone output imd vs. frequency, output level at 2 v p-p composite, r l = 200 and r l = 1 k 08003-028 0 5 10 15 20 25 30 35 40 45 50 ?2?1012345 oip3 (dbm) p out /tone (dbm) figure 13. output third-order intercept (oip3) vs. power (p out ), frequency 140 mhz, a v = 15.5 db ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ? 70 0 50 100 150 200 250 imd (dbc) frequency (mhz) a v maximum a v mid a v minimum 08003-007 figure 14. imd vs. freque ncy (single-ended input)
adl5562 rev. b | page 10 of 24 ?120 ?100 ?80 ?60 ?40 ?20 0 ?160 ?140 ?120 ?100 ?80 ?60 ? 40 0 50 100 150 200 250 harmonic distortion hd3 (dbc) harmonic distortion hd2 (dbc) frequency (mhz) a v maximum a v mid a v minimum 08003-021 figure 15. harmonic distortion (hd2/hd3) vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db, output level at 2 v p-p, r l = 200 ?120 ?100 ?80 ?60 ?40 ?20 0 ?160 ?140 ?120 ?100 ?80 ?60 ? 40 0 50 100 150 200 250 harmonic distortion hd3 (dbc) harmonic distortion hd2 (dbc) 08003-022 frequency (mhz) +85c +25c ?40c figure 16. harmonic distortion (hd2/hd3) vs. frequency, three temperatures, outp ut level at 2 v p-p, r l = 200 08003-023 ?120 ?100 ?80 ?60 ?40 ?20 0 ?160 ?140 ?120 ?100 ?80 ?60 ? 40 0 50 100 150 200 250 harmonic distortion hd3 (dbc) harmonic distortion hd2 (dbc) frequency (mhz) +85c +25c ?40c figure 17. harmonic distortion (hd2/h d3) vs. frequency, over temperature, output level at 2 v p-p, r l = 1 k ?120 ?100 ?80 ?60 ?40 ?20 0 ?160 ?140 ?120 ?100 ?80 ?60 ? 40 0 50 100 150 200 250 harmonic distortion hd3 (dbc) harmonic distortion hd2 (dbc) frequency (mhz) a v maximum a v mid a v minimum 0 8003-024 figure 18. harmonic distortion (hd2/hd3) vs. frequency at a v = 6 db, a v = 12 db, and a v = 15.5 db, output level at 2 v p-p, r l = 1 k 08003-029 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 ?2?1012345 harmonic distortion (dbc) hd2 hd3 p out (dbm) figure 19. harmonic distortion (hd2/hd3) vs. power (p out ), frequency 140 mhz, a v = 15.5 db ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ? 60 0 50 100 150 200 250 harmonic distortion hd3 (dbc) harmonic distortion hd2 (dbc) frequency (mhz) a v maximum a v mid a v minimum 08003-008 figure 20. harmonic distortion (hd2/hd3) vs. frequency (single-ended input)
adl5562 rev. b | page 11 of 24 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 0 100 200 300 400 500 600 700 800 900 1000 harmonic distortion hd3 (dbc) harmonic distortion hd2 (dbc) r load ( ? ) a v maximum a v mid a v minimum 08003-009 figure 21. harmonic distortion (hd2/hd3) vs. r load 08003-030 time (2.5ns/div) voltage (v) figure 22. enbl time domain response 08003-036 time (2.5ns/div) voltage (v) 2v p-p output figure 23. large signal pulse response, a v = 15.5 db ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ? 60 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ? 55 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 harmonic distortion hd3 (dbc) harmonic distortion hd2 (dbc) vcom (v) a v maximum a v mid a v minimum 08003-010 figure 24. harmonic distortion (hd2/hd3) vs. vcom ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 100 200 300 400 500 600 700 800 900 1000 phase (degrees) group del a y (ns) frequency (mhz) a v maximum a v mid a v minimum 08003-011 figure 25. group delay and phase vs. frequency 0 10 20 30 40 50 60 70 80 30 40 50 60 70 80 90 100 110 10m 100m 1g cmrr (db) cmrr (db) frequency (hz) a v maximum a v mid a v minimum r l = 200 ? r l = 1k ? 08003-012 figure 26. common-mode rejection ratio (cmrr) vs. frequency
adl5562 rev. b | page 12 of 24 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 s12 (db) frequency (ghz) disabled enabled 0 8003-013 figure 27. reverse isolation (s12) vs. frequency ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 0 100 200 300 400 500 600 700 800 900 1k 10m 100m 1g impedance phase (degrees) impedance magnitude ( ? ) frequency (hz) a v maximum a v mid a v minimum 08003-014 figure 28. input impedance vs. frequency 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 10m 100m 1g impedance phase (degrees) impedance magnitude ( ? ) freequency (hz) a v maximum a v mid a v minimum 08003-015 figure 29. output im pedance vs. frequency
adl5562 rev. b | page 13 of 24 circuit description basic structure the adl5562 is a low noise, fully differential amplifier/adc driver that uses a 3.3 v supply. it provides three gain options (6 db, 12 db, and 15.5 db) without the need for external resistors and has wide bandwidths of 2.6 ghz for 6 db, 2.3 ghz for 12 db, and 2.1 ghz for 15.5 db. differential input impedance is 400 for 6 db, 200 for 12 db, and 133 for 15.5 db. it has a differential output impedance of 10 and a common-mode adjust voltage of 1.25 v to 1.85 v. 08003-032 r l 1 / 2 r s 1 / 2 r s ac 200 ? 400 ? 0.1 f 0.1 f 400 ? 200 ? 100 ? 100 ? vip2 vip1 vin1 vin2 5 ? 5 ? + + figure 30. basic structure the adl5562 is composed of a fully differential amplifier with on-chip feedback and feed-forward resistors. the two feed-forward resistors on each input set this pin-strappable amplifier in three different gain configurations of 6 db, 12 db, and 15.5 db. the amplifier is designed to provide high differential open-loop gain and an output common-mode circuit that enables the user to change the common-mode voltage from a vcom pin. the amplifier is designed to provide superior low distortion at frequencies up to and beyond 300 mhz with low noise and low power consumption. the low distortion and noise are realized with a 3.3 v power supply at 80 ma. the adl5562 is very flexible in terms of i/o coupling. it can be ac-coupled or dc-coupled at the inputs and/or the outputs within the specified input and output common-mode levels. the input of the device can be configured as single-ended or differential with similar distortion performance. due to the internal connections between the inputs and outputs, keep the output common-mode voltage between 1.25 v and 1.85 v for the best distortion. for a dc-coupled input, the input common mode should be between 1 v and 2.3 v for the best distortion. the device has been characterized using 2 v p-p into 200 . if the inputs are ac-coupled, the input and output common-mode voltages are set by vcc/2 when no external circuitry is used. the adl5562 provides an output common-mode voltage set by vcom, which allows driving an adc directly without external components, such as a transformer or ac coupling capacitors, provided the vcom of the amplifier is within the vcom of the adc. for dc-coupled requirements, the input vcm must be set by the vcom pin in all three gain settings.
adl5562 rev. b | page 14 of 24 applications information basic connections figure 31 shows the basic connections for operating the adl5562. vcc should be 3.3 v with each supply pin decoupled with at least one low inductance surface-mount ceramic capacitor of 0.1 f placed as close as possible to the device. the vcom pin (pin 9) should also be decoupled using a 0.1 f capacitor. the gain of the part is determined by the pin-strappable input configuration. when input a is applied to vip1 and input b is applied to vin1, the gain is 6 db (minimum gain, see equation 1 and equation 2). when input a is applied to vip2 and input b is applied to vin2, the gain is 12 db (middle gain). when input a is applied to vip1 and vip2 and input b is applied to vin1 and vin2, the gain is 15.5 db (maximum gain). pin 1 to pin 4, pin 10, and pin 11 are biased at 1/2 vcc above ground and can be dc-coupled (if within the specified input or output common-mode voltage levels) or ac-coupled as shown in figure 31 . to enable the adl5562, the enbl pin must be pulled high. pulling the enbl pin low puts the adl5562 in sleep mode, reducing the current consumption to 3 ma at ambient. 1 2 3 4 11 12 10 9 5 6 7 8 1 5 1 6 1 4 1 3 vip2 vip1 vin1 vin2 vop enbl von vcom v c c v c c v c c v c c a c v c c g n d g n d g n d g n d adl5562 vcc balanced load r l 0.1f 0.1f a b 0.1f 10f 0.1f r s /2 r s /2 balanced source 0 8003-033 figure 31. basic connections
adl5562 rev. b | page 15 of 24 input and output interfacing the adl5562 can be configured as a differential-input to differential-output driver, as shown in figure 32 . the differential broadband input is provided by the etc1-1-13 balun transformer, and the two 34.8 resistors provide a 50 input match for the three input impedances that change with the variable gain strapping. the input and output 0.1 f capacitors isolate the vcc/2 bias from the source and balanced load. the load should equal 200 to provide the expected ac performance (see the specifications section and the typical performance characteristics section). 3.3 v vip2 vip1 vin1 vin2 a b 50 ? ac r2 08003- 043 + + 0.1f etc1-1-13 0.1f + r1 + 0.1f 0.1f notes 1. for 6db gain (a v = 2), connect input a to vip1 and input b to vin1. 2. for 12db gain (a v = 4), connect input a to vip2 and input b to vin2. 3. for 15.5db gain (a v = 6), connect input a to both vip1 and vip2 and input b to both vin1 and vin2. r l 2 r l 2 figure 32. differential-input to differential-output configuration ale differential erination alue for igure gain (db) r1 () r2 () 6 28.7 28.7 12 33.2 33.2 15.5 40.2 40.2 the differential gain of the adl5562 is dependent on the source impedance and load, as shown in figure 33 . r l 200 ? 400 ? 400 ? 200 ? 100 ? 100 ? vip2 vip1 vin1 vin2 5 ? 5 ? 0 8003- 044 + + 0.1f 0.1f 2 r l 2 ac 1 / 2 r s 1 / 2 r s 0.1f + 0.1f + figure 33. differential input loading circuit the differential gain can be determined using the following formula. the values of r in for each gain configuration are shown in table 5 . l l in v r r r a + = 10 400 (1) table 5. values of r in for differential gain gain (db) r in () 6 200 12 100 15.5 66.7 single-ended input to differential output the adl5562 can also be configured in a single-ended input to differential output driver, as shown in figure 34 . in this configuration, the gain of the part is reduced due to the application of the signal to only one side of the amplifier. the strappable gain values are listed in table 6 with the required terminations to match to a 50 source using r1 and r2. note that r1 must equal the parallel value of the source and r2. the input and output 0.1 f capacitors isolate the vcc/2 bias from the source and the balanced load. the performance for this configuration is shown in figure 11 , figure 14 , and figure 20 . vip2 vip1 vin1 vin2 a b 50 ? ac r2 08003-045 + + 0.1f 0.1f 0.1f 3.3 v + r1 notes 1. for 5.6db gain ( a v = 1.9), connect input a to vip1 and input b to vin1. 2 . for 11.1db gain ( a v = 3.6), connect input a to vip2 and input b to vin2. 3 . for 14.1db gain ( a v = 5.1), connect input a to both vip1 and vip2 and input b to both vin1 and vin2. + 0.1f r l 2 r l 2 figure 34. single-ended input to differential output configuration table 6. single-ended termination values for figure 34 gain (db) r1 () r2 () 5.6 27 60 11.1 29 69 14.1 30 77 the single-ended gain configuration of the adl5562 is dependent on the source impedance and load, as shown in figure 35 . r l 200 ? 400 ? 400 ? 200 ? 100 ? 100 ? vip2 vip1 vin1 vin2 5 ? 5 ? r s a c r2 0 8003- 046 + + 0.1f 0.1f 0.1f 0.1f + r1 + 2 r l 2 figure 35. single-ended input loading circuit
adl5562 rev. b | page 16 of 24 the single-ended gain can be determined using the following formula. the values of r in and r x for each gain configuration are shown in table 7 . the necessary shunt component, r shunt , to match to the source impedance, r s , can be expressed as in series s shunt rrr r + ? = 11 1 (4) l l x s x s s s in v r r r rr rr r rr rr r a + + + ? ? ? ? ? ? ? ? + + = 10 2 2 2 2 400 1 (2) the insertion loss and the resultant power gain for multiple shunt resistor values are summarized in table 8 . the source resistance and input impedance need careful attention when using equation 3 and equation 4. the reactance of the input impedance of the adl5562 and the ac coupling capacitors must be considered before assuming that they make a negligible contribution. table 7. values of r in and r x for single-ended gain gain (db) r in () r x () 5.6 200 r2 || 307 1 11.1 100 r2 || 179 1 14.1 66.7 r2 || 132 1 table 8. gain adjustment using series resistor 1 these values based on a 50 input match. il (db) r in () r s () r series () r shunt () 2 400 50 105 54.9 4 400 50 232 54.9 2 200 50 51.1 61.9 4 200 50 115 59 2 133 50 34.8 71.5 2 400 200 102 332 4 400 200 232 294 2 200 200 51.1 976 4 200 200 115 549 2 400 50 105 54.9 4 400 50 232 54.9 2 200 50 51.1 61.9 gain adjustment and interfacing the effective gain of the adl5562 can be reduced using a number of techniques. a matched attenuator network can reduce the effective gain; however, this requires the addition of a separate component that can be prohibitive in size and cost. instead, a simple voltage divider can be implemented using the combination of additional series resistors at the amplifier input and the input impedance of the adl5562, as shown in figure 36 . a shunt resistor is used to match to the impedance of the previous stage. 0.1f 08003-037 1 / 2 r shunt 1 / 2 r s 1 / 2 r s ac 0.1 f 1 / 2 r series vip1 vin2 v in1 vip2 1 / 2 r series 1 / 2 r shunt adl5562 adc interfacing the adl5562 is a high output linearity amplifier that is optimized for adc interfacing. there are several options available to the designer when using the adl5562. figure 37 shows a simplified wideband interface with the adl5562 driving the ad9445 . the ad9445 is a 14-bit, 125 msps adc with a buffered wideband input. figure 36. gain adjustment using a series resistor figure 36 shows a typical implementation of the divider concept that effectively reduces the gain by adding attenuation at the input. for frequencies less than 100 mhz, the input impedance of the adl5562 can be modeled as a real 133 , 200 , or 400 resistance (differential) for maximum, middle, and minimum gains, respectively. assuming that the frequency is low enough to ignore the shunt reactance of the input and high enough so that the reactance of moderately sized ac coupling capacitors can be considered negligible, the insertion loss, il, due to the shunt divider can be expressed as ? ? ? ? ? ? ? ? + = in series in rr r dbil log20) ( (3) for optimum performance, the adl5562 should be driven differentially using an input balun. figure 37 uses a wideband 1:1 transmission line balun followed by two 34.8 resistors in parallel with the three input impedances (which change with the gain selection of the ad55l62) to provide a 50 differential input impedance. this provides a wideband match to a 50 source. the adl5562 is ac-coupled from the ad9445 to avoid common- mode dc loading. the 33 series resistors help to improve the isolation between the adl5562 and any switching currents present at the analog-to-digital sample-and-hold input circuitry. the ad9445 input presents a 2 k differential load impedance and requires a 2 v p-p differential input swing to reach full scale (vref = 1 v). 0.1f 08003-038 34.8 ? 50? a c 0.1 f 3.3 v etc1-1-13 vin1 vip1 vip2 a b vin2 34.8 ? adl5562 + + 0.1f 0.1f 33 ? vop von 33 ? + + ad9445 14-bit adc 14 vin+ vin? figure 37. wideband adc interfacing example featuring the ad9445
adl5562 rev. b | page 17 of 24 this circuit provides variable gain, isolation, and source matching for the ad9445 . using this circuit with the adl5562 in a gain of 6 db, an sfdr performance of 87 dbc is achieved at 140 mhz, and a ?3 db bandwidth of 760 mhz, as indicated in figure 38 and figure 39 . 08003-026 0 6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25 62.50 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 (dbfs) frequency (mhz) adl5562 driving the ad9445 14-bit adc gain = 6db input = 140mhz snr = 66.25dbc sfdr = 87.44dbc noise floor = ?109.5db fund = ?1.081dbfs second = ?84.54dbc third = ?84.54dbc figure 38. measured single-tone performance of the circuit in figure 37 for a 100 mhz input signal 08003-025 frequency (mhz) first point = ?1.02dbfs end point = ?5.69dbfs mid point = ?1.09dbfs min = ?5.69dbfs max = ?0.88dbfs 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 2.00 81.90 241.70 401.50 561.30 721.10 161.80 321.60 481.40 641.20 801.00 (dbfs) figure 39. measured frequency response of the wideband adc interface depicted in figure 37 the wideband frequency response is an advantage in broad- band applications, such as predistortion receiver designs and instrumentation applications. however, by designing for a wide analog input frequency range, the cascaded snr performance is somewhat degraded due to high frequency noise aliasing into the wanted nyquist zone. an alternative narrow-band approach is presented in figure 40 . by designing a narrow band-pass antialiasing filter between the adl5562 and the target adc, the output noise of the adl5562 outside of the intended nyquist zone can be attenuated, helping to preserve the available snr of the adc. in general, the snr improves several decibels when including a reasonable order anti- aliasing filter. in this example, a low loss 1:1 input transformer is used to match the adl5562 balanced input to a 50 unbalanced source, resulting in minimum insertion loss at the input. figure 40 is optimized for driving some of the analog devices popular unbuffered adcs, such as the ad9246 , ad9640, and ad6655. table 9 includes antialiasing filter component recommendations for popular if sampling center frequencies. inductor l5 works in parallel with the on-chip adc input capacitance and a portion of the capacitance presented by c4 to form a resonant tank circuit. the resonant tank helps to ensure that the adc input looks like a real resistance at the target center frequency. the l5 inductor shorts the adc inputs at dc, which introduces a zero into the transfer function. in addition, the ac coupling capacitors introduce additional zeros into the transfer function. the final overall frequency response takes on a band- pass characteristic, helping to reject noise outside of the intended nyquist zone. table 9 provides initial suggestions for prototyping purposes. some empirical optimization may be needed to help compensate for actual pcb parasitics. 08003-039 105 ? l5 105 ? ad9246 ad9640 ad6655 1nf l1 c2 l3 1nf l1 l3 c4 cml adl5562 4 ? 4 ? figure 40. narrow-band if sampling solution for an unbuffered adc application table 9. interface filter recommendation s for various if sampling frequencies center frequency (mhz) 1 db bandwidth (mhz) l1 (nh) c2 (pf) l3 (nh) c4 (pf) l5 (nh) 96 30 3.3 47 27 75 100 140 33 3.3 47 27 33 120 170 32 3.3 56 27 22 110 211 33 3.3 47 27 18 56
adl5562 rev. b | page 18 of 24 layout considerations high-q inductive drives and loads, as well as stray transmission line capacitance in combinatio n with package parasitics, can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. if rf transmission lines connecting the input or output are used, they should be designed such that stray capacitance at the input/output pins is minimized. in many board designs, the signal trace widths should be minimal where the driver/receiver is more than one- eighth of the wavelength from the amplifier. this nontransmission line configuration requires that underlying and adjacent ground and low impedance planes be dropped from the signal lines 0.1f 0.1f 0.1f 0.1f adl5562 vip2 vip1 vin1 vop von vin2 r6 r5 r4 r3 r2 r1 r8 r7 r10 r9 etc1-1-13 etc1-1-13 spectrum analyzer 08003-034 figure 41. general purpose characterization circuit table 10. gain setting and input termination components for figure 41 a v (db) r1 () r2 () r3 () r4 () r5 () r6 () 6 29 29 open 0 0 open 12 33 33 0 open open 0 15.5 40.2 40.2 0 0 0 0 table 11. output matching network for figure 41 r l () r7 () r8 () r9 () r10 () 200 84.5 84.5 34.8 34.8 1 k 487 487 25 25 adl5562 vip2 vip1 vin1 vop von vin2 r6 r5 r4 r3 r2 r1 r8 r7 r10 r9 port 1 port 3 port 2 port 4 0 8003-035 figure 42. differential characterization circuit using agilent e8357a 4-port pna table 12. gain setting and input termination components for figure 42 a v (db) r1 () r2 () r3 () r4 () r5 () r6 () 6 67 67 open 0 0 open 12 100 100 0 open open 0 15.5 200 200 0 0 0 0 table 13. output matching network for figure 42 r l () r7 () r8 () r9 () r10 () 200 50 50 open open 1 k 475 475 61.9 61.9
adl5562 rev. b | page 19 of 24 soldering information on the underside of the chip scale package, there is an exposed compressed paddle. this paddle is internally connected to the ground of the chip. solder the paddle to the low impedance ground plane on the pcb to ensure the specified electrical performance and to provide thermal relief. to further reduce thermal impedance, it is recommended that the ground planes on all layers under the paddle be stitched together with vias. evaluation board figure 43 shows the schematic of the adl5562 evaluation board. the board is powered by a single supply in the 3 v to 3.6 v range. the power supply is decoupled by 10 f and 0.1 f capacitors. table 14 details the various configuration options of the evaluation board. figure 44 and figure 45 show the component and circuit layouts of the evaluation board. to realize the minimum gain (6 db into a 200 load), input 1 (vin1 and vip1) must be used by installing 0 resistors at r3 and r4, leaving r5 and r6 open. r1 and r2 must be 33 for a 50 input impedance. likewise, driving input 2 (vin2 and vip2) realizes the middle gain (12 db into a 200 load) by installing 0 at r5 and r6 and leaving r3 and r4 open. r1 and r2 must be 29 for a 50 input impedance. for the maximum gain (15.5 db into a 200 load), both inputs are driven by installing 0 resistors at r3, r4, r5, and r6. r1 and r2 must be 40.2 for a 50 input impedance. the balanced input and output interfaces are converted to single ended with a pair of baluns (m/a-com etc1-1-13). the balun at the input, t1, provides a 50 single-ended-to- differential transformation. the output balun, t2, and the matching components are configured to provide a 200 to 50 impedance transformation with an insertion loss of about 17 db. c3 10f c4 0.1f c5 0.1f c6 0.1f c7 0.1f c8 0.1f c13 0.1f c11 0.1f vpos 08003-040 r9 34.8 ? r11 open j3 r10 34.8 ? r8 84.5 ? c10 0.01f c9 0.01f p1 t2 j2 agnd vpos gnd r7 84.5 ? enbl adl5562 9 10 11 12 4 3 2 1 16 15 14 13 5678 gnd gnd gnd gnd vcc vin1 vin2 vip2 vip1 von vocm enbl vop vcc vcc vcc c12 0.1f j 1 t1 r1 40.2 ? r2 40.2 ? r4 0 ? r3 0 ? r5 0 ? r6 0 ? c1 0.01f c2 0.01f figure 43. evaluation board schematic table 14. evaluation board configuration options component description default condition vpos, gnd ground and supply vect or pins. vpos, gnd = installed c3, c4, c5, c6, c7, c11 power supply decoupling. the supply decoupling consists of a 10 f capacitor (c3) to ground. c4 to c7 are bypass capacitors. c11 ac couples vref to ground. c3 = 10 f (size d), c4, c5, c6, c7, c11 = 0.1 f (size 0402) j1, r1, r2, r3, r4, r5, r6, c1, c2, c12, t1 input interface. the sma labeled j1 is the input. t1 is a 1-to-1 impedance ratio balun to transform a single-ended input into a balanced differential signal. c1 and c2 provide ac coupling. c12 is a bypass capacitor. r1 and r2 provide a differential 50 input termination. r3 to r6 are used to se lect the input for the pin-strappable gain. maximum gain: r3, r4, r5, r6 = 0 ; and r1, r2 = 40.2 . middle gain: r5, r6 = 0 ; and r3, r4 = open; r1, r2 = 33 . minimum gain: r3, r4 = 0 ; and r5, r6 = open; r1, r2 = 29 . j1 = installed, r1, r2 = 40.2 (size 0402), r3, r4, r5, r6 = 0 (size 0402), c1, c2 = 0.01 f (size 0402), c12 = 0.1 f (size 0402) t1 = etc1-1-13 (m/a-com) j3, r7, r8, r9, r10, r11, c9, c10, c13, t2 output interface. the sma labeled j3 is the output. t2 is a 1-to-1 impedance ratio balun to transform a balanced differential signal to a single-ended signal. c13 is a bypass capacitor. r7, r8, r9, and r10 are provided for generic placement of matching components. the evaluation board is configur ed to provide a 200 to 50 impedance transformation with an insertion loss of 17 db. c9 and c10 provide ac coupling. j3 = installed, r7, r8 = 84.5 (size 0402), r9, r10 = 34.8 (size 0402), r11 = open (size 0402), c9, c10 = 0.01 f (size 0402), c13 = 0.1 f (size 0402) t2 = etc1-1-13 (m/a-com) enbl, p1, c8 device enable. c8 is a bypass capacitor. when the p1 jumper is set toward the vpos label, the enbl pin is connected to the supply, enabling the device. in the opposite direction, toward the gnd label, the enbl pin is ground ed, putting the device in power-down mode. enbl, p1= installed, c8 = 0.1 f (size 0402)
adl5562 rev. b | page 20 of 24 08003-041 figure 44. layout of evaluation board, component side 08003-042 figure 45. layout of evaluation board, circuit side
adl5562 rev. b | page 21 of 24 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 072208-a figure 46. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ordering quantity adl5562acpz-r7 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_vq], 7 reel cp-16-2 q1q 1,500 ADL5562ACPZ-WP ?40c to +85c 16-lead lead frame chip scale package [lfcsp_vq], waffle pack cp-16-2 q1q 50 adl5562-evalz evaluation board 1 z = rohs compliant part.
adl5562 rev. b | page 22 of 24 notes
adl5562 rev. b | page 23 of 24 notes
adl5562 rev. b | page 24 of 24 notes ?2009C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08003-0-3/10(b)

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